The present invention relates to a method of forming well-shaped, boron-doped regions in a semiconductor substrate, whereby a desired retrograde boron concentration distribution profile is obtained. The present invention has particular utility in the manufacture of MOS-type transistor devices and semiconductor integrated circuits with improved processing methodology resulting in increased reliability and quality, increased manufacturing throughput, and reduced fabrication cost. The present invention is also useful in the manufacture of CMOS semiconductor devices and has particular applicability in fabricating high-density integration semiconductor devices with design features below about 0.18 xcexcm, e.g., about 0.15 xcexcm.
The escalating requirements for high density and performance associated with ultra large scale integration (ULSI) semiconductor devices requires design features of 0.18 xcexcm and below, such a 0.15 xcexcm and below, increased transistor and circuit speeds, high reliability, and increased manufacturing throughput for economic competitiveness. The reduction of design features to 0.18 xcexcm and below challenges the limitations of conventional semiconductor manufacturing techniques.
As feature sizes of MOS and CMOS devices have decreased to the sub-micron range, so-called xe2x80x9cshort-channelxe2x80x9d effects have arisen which tend to limit device performance. For n-channel MOS transistors, the major limitation encountered is caused by hot-electron-induced instabilities. This problem occurs due to high electrical fields between the source and the drain, particularly near the drain, such that charge carriers, either electrons or holes, are injected into the gate or semiconductor substrate. Injection of hot carriers into the gate can cause gate oxide charging and threshold voltage instabilities which accumulate over time and greatly degrade device performance. In order to counter and thus reduce such instabilities, shallow junction, lightly- or moderately-doped source/drain extension-type transistor structures have been developed, as described below.
For p-channel MOS transistors, the major xe2x80x9cshort-channelxe2x80x9d effect which limits performance arises from xe2x80x9cpunch-throughxe2x80x9d effects which occur with relatively deep junctions. In such instances, there is a wider sub-surface depletion effect and it is easier for the field lines to go from the drain to the source, resulting in the above-mentioned xe2x80x9cpunch-throughxe2x80x9d current problems and device shorting. To minimize this effect, relatively shallow junctions are employed in forming p-channel MOS-type transistors.
The most satisfactory solution to date of hot carrier instability problems of MOS- and CMOS-type devices is the provision of lightly- or moderately-doped source/drain extensions driven just under the gate region, while the heavily-doped source/drain regions are laterally displaced away from the gate by use of a pair of spacers on opposite sidewalls of the gate. Such structures are particularly advantageous because they do not have problems with large lateral diffusion and the channel length can be set precisely.
However, in the case of p-channel MOS and CMOS devices, formation of p-type junctions having desired characteristics (e.g., depth, doping concentration profiles, etc.) by boron doping is problematic, principally due to the ease with which boron atoms diffuse in silicon semiconductor substrates. The rapidity of boron dopant atom diffusion upon thermal treatment for post-implantation activation/lattice damage relaxation disadvantageously results in a relatively flat concentration distribution profile, whereas a retrograde concentration distribution profile, i.e., a profile exhibiting a maximum or peak boron concentration at a preselected depth below the semiconductor substrate surface, is desirable and preferred for suppression of xe2x80x9cshort-channelxe2x80x9d effects and maintenance of high channel mobility.
Thus a need exists for improved semiconductor manufacturing methodology for fabricating p-channel MOS and CMOS transistors which does not suffer from the above-described drawback associated with the rapid diffusion of boron atoms in silicon semiconductor substrates. Moreover, there exists a need for an improved process for fabricating MOS transistor-based devices with reduced short-channel effects and high channel mobility, which process is fully compatible with conventional process flow and provides increased manufacturing throughput and product yield.
The present invention fully addresses and solves the above-described drawback attendant upon conventional processing for forming submicron-dimensioned p-channel MOS and CMOS transistors for use in high-density integrated semiconductor devices, particularly in providing a process for forming boron-doped p-type wells in silicon semiconductor substrates, wherein the boron concentration distribution profile is advantageously retrograde-shaped, with a maximum or peak boron concentration at a preselected depth below the substrate surface, whereby xe2x80x9cshort-channelxe2x80x9d effects are suppressed while maintaining high channel mobility.
An advantage of the present invention is an improved method for forming a boron-doped region in a semiconductor substrate, having a preselected maximum or peak boron concentratioh at a preselected depth below the surface of the substrate.
Another advantage of the present invention is an improved method for forming a boron-doped region in a semiconductor substrate, having a retrograde-shaped boron concentration distribution profile with a maximum or peak boron concentration at a preselected depth below the substrate surface.
Still another advantage of the present invention is an improved method for manufacturing a MOS transistor having at least one pair of boron-doped, well-shaped regions formed in a semiconductor substrate, each of the boron-doped well regions having a retrograde-shaped boron concentration distribution profile with a maximum or peak boron concentration at a preselected depth below the substrate surface.
Yet another advantage of the present invention is a silicon-based, MOS-type transistor device comprising boron-doped well regions each having a retrograde-shaped boron concentration distribution profile with a maximum or peak boron concentration at a preselected depth below the surface of a silicon semiconductor substrate and formed by the method of the present invention.
Additional advantages and other features of the present invention will be set forth in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the instant invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to an aspect of the present invention, the foregoing and other advantages are achieved in part by a method of forming a boron-doped region in a semiconductor, the boron-doped region having a retrograde-shaped boron concentration distribution profile exhibiting a maximum or peak boron concentration at a preselected depth below a surface of the semiconductor, which method comprises the steps of:
(a) providing a semiconductor having a surface;
(b) implanting nitrogen ions into the semiconductor surface, the implantation conditions chosen for providing a preselected, approximately parabolically-shaped nitrogen concentration distribution profile within the semiconductor with a peak nitrogen concentration at a depth below the semiconductor surface substantially corresponding to the preselected depth;
(c) implanting boron or boron-containing ions into the semiconductor surface, the implantation conditions chosen for providing a preselected, approximately parabolically-shaped boron concentration distribution profile within the semiconductor with a peak boron concentration at a depth below the semiconductor surface which is above, below, or substantially at the depth of the nitrogen concentration peak; and
(d) thermally treating the nitrogen- and boron-implanted semiconductor at a temperature and for an interval sufficient to convert the parabolically-shaped boron concentration distribution profile into a retrograde-shaped profile comprising, in order from the semiconductor surface, a first, substantially constant (i.e., flat) concentration portion, a second, substantially parabolically-shaped varying concentration portion having a peak, and a third, substantially constant concentration portion, wherein the peak of the second, parabolically-shaped varying concentration portion substantially corresponds to the preselected depth below the semiconductor surface.
In embodiments according to the present invention, the boron concentrations in the first and third substantially constant concentration portions of the retrograde profile are approximately equal, and step (b) is performed prior to step (c), or alternatively, step (c) is performed prior to step (b).
In further embodiments according to the present invention, step (a) comprises providing a monocrystalline silicon (Si) semiconductor wafer of n-type or intrinsic (i.e., i-type) conductivity; the preselected depth of the peak boron concentration is about 800 A below the wafer surface; step (b) comprises implanting N+ or N2+ ions at a dosage of from about 1xc3x971014 to about 3xc3x971015 atoms/cm2 at an energy of from about 2 KeV to about 50 KeV; step (c) comprises implanting B+ or BF2+ ions at a dosage of from about 1xc3x971012 to about 5xc3x971013 atoms/cm2 at an energy of from about 2 KeV to about 50 KeV; and step (d) comprises rapid thermal annealing (RTA) at from about 850 to about 1,050xc2x0 C. for from about 1 to about 30 seconds or furnace annealing at from about 750 to about 900xc2x0 C. for from about 5 minutes to about 1 hour.
According to another aspect of the present invention, a method of manufacturing a semiconductor device is provided, the semiconductor device comprising a semiconductor substrate having at least one pair of spaced-apart, boron-doped regions formed therein, each of the boron-doped regions having a retrograde-shaped boron concentration distribution profile exhibiting a peak boron concentration at a preselected depth below a surface of the semiconductor substrate, which method comprises the steps of:
(a) providing an n-type semiconductor wafer having a surface;
(b) implanting nitrogen ions into at least a pair of preselected, spaced-apart regions of said semiconductor wafer surface where source/drain regions are to be formed, the implantation conditions chosen for providing each of the implanted regions with a preselected, approximately parabolically-shaped nitrogen concentration distribution profile, with a peak nitrogen concentration at a depth below the semiconductor wafer surface substantially corresponding to the preselected depth;
(c) implanting boron or boron-containing ions into the preselected, spaced-apart regions of the semiconductor wafer surface, the implantation conditions chosen for providing each of the implanted regions with a preselected, approximately parabolically-shaped boron concentration distribution profile, with a peak boron concentration at a depth below the semiconductor wafer surface which is above, below, or substantially at the depth of the nitrogen concentration peak;
(d) thermally treating the nitrogen and boron-implanted semiconductor wafer at a temperature and for an interval sufficient to convert the parabolically-shaped boron concentration distribution profile of each of the implanted regions into a retrograde-shaped profile comprising, in order from the semiconductor wafer surface, a first, substantially constant concentration portion, a second, substantially parabolically-shaped varying concentration portion having a peak, and a third, substantially constant concentration portion, wherein the peak of the second, parabolically-shaped varying concentration portion substantially corresponds to the preselected depth below the semiconductor wafer surface; and
(e) selectively forming a gate insulating layer on a preselected portion of the semiconductor wafer surface intermediate the implanted regions.
According to embodiments of the present invention, step (e) comprises selectively removing portions of an insulating layer formed over the semiconductor wafer surface during step (d); the inventive method further comprises the step (f) of forming a gate electrode layer contiguous with and in ohmic contact with the gate insulating layer; and the boron concentrations in the first and third portions of the retrograde-shaped profile are substantially equal.
According to further embodiments of the invention, step (a) comprises providing a monocrystalline Si wafer of n-type conductivity; step (b) is performed prior to performing step (c), or alternatively, step (c) is performed prior to performing step (b); the preselected depth of the peak boron concentration is about 800 A below the wafer surface; step (b) comprises implanting N+ or N2+ ions at a dosage of from about 1xc3x971014 to about 3xc3x971015 atoms/cm2 at an energy of from about 2 KeV to about 50 KeV; step (c) comprises implanting B+ or BF2+ ions at a dosage of from about 1xc3x971012 to about 5xc3x971013 atoms/cm2 at an energy of from about 2 KeV to about 50 KeV; step (d) comprises rapid thermal annealing at from about 850 to about 1,050xc2x0 C. for from about 1 to about 30 seconds, or alternatively, step (d) comprises furnace annealing at from about 750 to about 900xc2x0 C. for from about 5 minutes to about 1 hour, preferably in an oxygen-containing atmosphere for forming a silicon oxide insulating layer over the wafer surface; step (e) comprises selectively removing portions of the silicon oxide insulating layer to form the gate insulating layer intermediate the implanted regions of the wafer; and step (f) comprises forming a heavily-doped polysilicon gate electrode layer.
According to yet another aspect according to the present invention, silicon-based MOS transistor devices formed by the method comprising the above-enumerated steps (a)-(f) are provided.
Additional advantages and aspects of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will become evident, the present invention is capable of other and different embodiments, and its several details are susceptible of modification in various obvious respects, all without departing from the spirit of the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.